| 摘要 |
PROBLEM TO BE SOLVED: To improve an ESD protection circuit without increasing the total processes by applying a local ion implantation process and improving a large current capacity of an NMOS transistor actuated by a lateral npn bipolar transis tor mode during electrostatic discharge(ESD) phenomena. SOLUTION: In an implantation process for manufacturing CMOS structure provided with an ESD (ESD HVnMOS), an (n) well area is covered with a mask, P-well is implanted to form a p-well. Secondly, the (n) channel is implanted with the (n) well area covered, and Vtn1, Yptn, and CSn are executed. For a dual voltage design, the implantation Vtn to a low voltage sets a second threshold voltage. The hole current of the ESD device having an avalanche passes a material doped by implantation of P-well, Vtin1, Vptn, and CSn and lastly flows through a substrate (LVnMOS).
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