发明名称 CASCADE A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To perform linearity adjustment at high speed in simple circuit configuration by finding an adjustment quantity through a detecting means by determining a circuit to be adjusted on the basis of the output of an analog multiplexer circuit, and adjusting a subtracter or D/A converter on the basis of the output of the detecting means. SOLUTION: Outputs from the analog multiplexer are converted by an A/D converter 21, selected by a multiplexer circuit 22 on the basis of the timing of a control signal 103 and successively stored in storage circuits 23a-23c. The multiplexer circuit 22 is controlled so as to fetch the output of the analog multiplexer circuit at the time of a value at the prescribed position of an analog input signal as the control signal 103. An arithmetic circuit 24 successively reads values stored in the storage circuits 23a-23c, determines the circuit to be adjusted and finds the quantity of that adjustment. Plural D/A converters 25a-25f for supplying an adjust signal to the circuit to be adjusted are controlled and the found adjustment quantity is impressed to this circuit.
申请公布号 JP2000209092(A) 申请公布日期 2000.07.28
申请号 JP19990009271 申请日期 1999.01.18
申请人 YOKOGAWA ELECTRIC CORP 发明人 IRIE KOICHI;KUSAYANAGI NAOYA
分类号 H03M1/14;H03M1/06;H03M1/44;(IPC1-7):H03M1/14 主分类号 H03M1/14
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