| 摘要 |
PROBLEM TO BE SOLVED: To obtain a wafer in which test accuracy can be enhanced by suppressing the difference of I/O response during test time and during normal operation. SOLUTION: Since a test signal output line 31 connected in parallel with a corresponding normal signal output line 26 and outputting a test signal processed through a flash memory 21 to a dedicated pad 5 through an inverter 32 is provided, the test signal is outputted to the dedicated pad 5 and a normal pad 4 through an arrangement having identical characteristics during test time and during normal operation. Since no difference appears in I/O response during test time and during normal operation, test can be carried out accurately.
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