| 摘要 |
PROBLEM TO BE SOLVED: To surely detect the there is a risk of short circuiting between wiring, in a semiconductor integrated circuit. SOLUTION: A test element group consists of a plurality of parallel lower- layer wiring 12 formed a the upper portion of a substrate, where a semiconductor integrated circuit is formed, an interlayer insulating film 13 for covering the area between the lower layer wiring and an upper portion, and comb-shaped upper-layer wiring 14 and 15 which is formed on the interlayer insulating film 13, while opposing each other independently. An interval G of the lower-layer wiring 12 is formed, while being changed. Although the test element group is made to generate etching remainder at the upper-layer wirings 14 and 15 due to the level difference caused by the lower-layer wiring 12 for indicating the presence or absence of the short-circuiting between wiring, the state of a plurality of types of level differences to the upper-layer wiring 14 and 15 for setting the worst state can be set by changing the interval G of the lower- layer wiring 12.
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