| 摘要 |
<p>A control resister (41) holds control data according to an instruction given externally. A parallelism control unit (40) determines the parallelism of the parallel operation of data processing sections (20-1 to 20-n) according to the control data held by the control resister (41). Another control resister (32) controls the frequency of the operating clock signal (CLK) for the data processing sections according to the preset control data. Since the parallelism and operating speed of the data processing sections are thus controlled according to external conditions, the processing capacity and power consumption of the data processing sections are also readily controlled according to external state. Changing the parallelism of the data processing sections is suitable for the control prior to a series of processings. It is possible to change the clock frequency even during a series of processings.</p> |
