| 摘要 |
PROBLEM TO BE SOLVED: To output complementary output signals, consisting of a positive phase and a negative phase without time difference by providing first and second switches MOSFET to be a turned-on state in one of the level periods of each clock signal between the output terminals of first and second inverter circuits and first and second internal nodes. SOLUTION: Switches MOSFET Q3 and Q4, to be turned-on in one of the level periods of each clock signal CK, are arranged between the output terminals of the inverter circuits IV 3 and 4 and the internal nodes 205 and 204. Moreover, the switches MOSFET Q1 and Q2 are disposed, which are turned on in the other level period of the clock signal CK to transmit an input signal D and its reverse signal to the internal nodes 204 and 205. Inverter circuits IV5 and IV6 for generating output signals by receiving the signal of 205 are arranged, the output signals are supplied to the same kind of circuits and an input and a holding operation are executed complementarily by the clock signal CK. Thus, the output signals of the positive and negative phases are outputted at high speed.
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