| 摘要 |
An integrated semiconductor circuit arrangement includes a substrate (2) of a first conductivity type (p), on which are arranged at least one first zone (4) of a second conductivity type (n) for connection of a first supply potential (+U), and at least one second zone (6) of the second conductivity type (n) for connection of a second reference potential (A). A third zone (8) is arranged on the substrate (2) and is of the second conductivity type (n) for connection to an output terminal (A). A fourth zone (10) of the first conductivity type (p) is arranged between the first (4) and third (8) zones on the substrate, and a fifth zone (12) of the first conductivity type (p) is arranged on the substrate between the second (6) and the third (8) zones. Control electrodes (16,20) are separated from the fourth and fifth zones by insulation layers (18,22) and at least one control electrode (16) is arranged over the fourth zone (10) and at least one control electrode (20) is arranged over the fifth zone (12).
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