| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device, capable of shortening the period for development by providing a clock synchronous DRAM in multi- bank configuration, while utilizing a clock asynchronous DRAM. SOLUTION: A clock synchronous DRAM 1 has a command decoding circuit 2, an access control circuit 3 and plural banks 0-n respectively composed of clock asynchronous DRAM. The command decode circuit 2 decodes the access command of the clock synchronous DRAM and decodes an operating mode. The access control circuit 3 receives the decoded result of the operating mode from the command decode circuit 2 and controls the clock asynchronous DRAM according to this result. Concerning the parallel operation of the banks 0 to n also, the command decode circuit 2 decides how to operate the banks in parallel as well and the access control circuit 3 makes access to the respective banks 0-n.
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