发明名称 METHOD FOR DESIGNING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To arrange a bypass capacitor of an optimum capacitance value at an optimum position while verifying an effect in detail and to reduce noise involved in power supply fluctuations. SOLUTION: This method is to design a noise reduction operation circuit by connecting one or more bypass capacitors 24 to an IC or the like such as, e.g. one VLSI, LSI or IC 26, temporarily sets the capacitor and arrangement place of the capacitors 24, and subsequently performs arithmetic processing of an impedance-frequency characteristic in a current path including the capacitors on the basis of a prescribed formula by a central processing unit (computer) 18 to display a frequency characteristic graph on the screen of a display device 14. Also, a designer views and evaluates the frequency characteristic graph displayed on the device 14 and decides the optimum capacitance value of the bypass capacitors by repeating this operating until an operation frequency fa comes close to a resonance frequency fr.
申请公布号 JP2001175702(A) 申请公布日期 2001.06.29
申请号 JP19990363804 申请日期 1999.12.22
申请人 SANYO ELECTRIC CO LTD 发明人 UMAGAMI KEIICHI;OKUMA TOSHIAKI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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