发明名称 PAIR ARRANGEMENT RULE CHECK METHOD AND STORAGE MEDIUM
摘要 PROBLEM TO BE SOLVED: To improve the yield of a semiconductor integrated circuit device by automatically making a rule check on elements constituting a pair and reducing characteristic defects of an analog circuit. SOLUTION: The distance between elements constituting a pair generated according to circuit diagram data and pair information is calculated. It is decided whether or not the element distance is larger than a rule value and when so, the names of the elements constituting the pair and the element distance are stored as an element distance rule violation. Then the parallelism of the pair is retrieved from a pair arrangement rule, and rotation parameters of the elements constituting the pair are retrieved from layout data and compared according to the pair arrangement rule to judge whether or not their directions are the same. When the directions are not the same, the name of the elements constituting the pair and the rotation parameters of the elements are stored as an identical directivity violation. After all pairs are checked, those violation data are displayed on the display.
申请公布号 JP2001175700(A) 申请公布日期 2001.06.29
申请号 JP19990359865 申请日期 1999.12.17
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 ARAI KAORI;FUKUDA MASANORI;FUKAMACHI TOSHIYUKI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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