发明名称 POTENTIAL GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce current consumption. SOLUTION: The potential generation circuit is provided with operational amplifiers OP1-OP3, a PMOS transistor(TR) PT1 and an NMOS TR NT1. When the potential of a terminal OUT1 is dropped, the amplifier OP2 supplies an L level signal to the TR PT1, which is turned on. Thereby a current is supplied from a power supply node VDD to the terminal OUT1. When the potential of the terminal OUT1 is raised, the amplifier OP3 supplies an H level signal to the TR NT1, which is turned on. Thereby a current is led from the terminal OUT1 into a ground node GND.
申请公布号 JP2001175340(A) 申请公布日期 2001.06.29
申请号 JP19990354537 申请日期 1999.12.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KOMATSU YOSHIHIDE;AKAMATSU HIRONORI;HIRATA TAKASHI;TAKAHASHI SATOSHI;TERADA YUTAKA
分类号 G05F1/10;G05F3/20;(IPC1-7):G05F1/10 主分类号 G05F1/10
代理机构 代理人
主权项
地址