| 摘要 |
PROBLEM TO BE SOLVED: To operate a memory at high speed corresponding to a mixed high speed logic circuit when a cost reduction is planned by using a DRAM of three transistor cells requiring no capacitor. SOLUTION: In a pair of data line formed by connecting plural memory cells having an amplifying function, a dummy cell is unnecessitated by setting respective data line pre-charge voltage in the pair line to difference values. As the dummy cell being indispensable hitherto in a DRAM using a gain cell is made unnecessary, such effects are obtained that area is reduced and a manufacturing cost is reduced. Also high speed operation can be performed by making the circuit as hierarchcical data line structure. Also, A DRAM circuit can be made by using a manufacturing process being consistent with an ordinary logic element.
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