发明名称 Clock and data recovery scheme for multi-channel data communications receivers
摘要 The multiple-channel clock and data recovery scheme of the present invention derives a single clock signal from multiple mis-matched data streams. The single clock is phased to provide a clocking signal such that the data sampler of the clock and data recovery scheme performs bit center sampling of the data at the bit center average of all channels. The phase of the recovery clock is the average of all the data stream phases, and is the optimal sampling phase for minimum combined bit error rate of all the channels.
申请公布号 US6307906(B1) 申请公布日期 2001.10.23
申请号 US19980168028 申请日期 1998.10.07
申请人 APPLIED MICRO CIRCUITS CORPORATION 发明人 TANJI TODD M.;WELCH JAMES R.
分类号 H03D13/00;H03L7/087;H03L7/089;H03L7/091;H03L7/099;H04L7/033;H04L25/14;(IPC1-7):H03D11/06 主分类号 H03D13/00
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