发明名称 HIGH-SPEED LOW-POWER SEMICONDUCTOR MEMORY ARCHITECTURE
摘要 An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
申请公布号 WO0203459(A2) 申请公布日期 2002.01.10
申请号 WO2001US19896 申请日期 2001.06.22
申请人 MOSAIC SYSTEMS, INC. 发明人 ALEXANIAN, SUREN, A.
分类号 G11C11/41;G06F7/38;G11C5/02;G11C5/06;G11C7/00;G11C7/18;G11C8/00;G11C8/12;G11C11/401;G11C11/413;G11C16/06;H01L21/8239;H01L27/105;H03K19/177 主分类号 G11C11/41
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