发明名称 |
Clock generation circuit, control method of clock generation circuit and semiconductor memory device |
摘要 |
A clock duty adjusting circuit is provided in the subsequent stage of a variable delay circuit to control the delay of the variable delay circuit with the rising edge of clock. When the phase of the rising edge is matched with the reference clock, the duty of output clock is matched with the duty of the reference clock by adjusting the pulse width of the signal with the duty adjusting circuit at the falling edge.
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申请公布号 |
US2002008558(A1) |
申请公布日期 |
2002.01.24 |
申请号 |
US20010908857 |
申请日期 |
2001.07.20 |
申请人 |
OKUDA YUICHI;CHIGASAKI HIDEO;MIYASHITA HIROKI |
发明人 |
OKUDA YUICHI;CHIGASAKI HIDEO;MIYASHITA HIROKI |
分类号 |
G11C11/407;G06F1/06;G11C7/10;H03K5/00;H03K5/04;H03K5/13;H03K5/156;H03L7/081;H03L7/087;H03L7/089;H03L7/107;H03L7/113;(IPC1-7):H03K3/017 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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