| 摘要 |
PROBLEM TO BE SOLVED: To make the verification of all the scan path F/F holding times for a product LSI able to be surely carried out. SOLUTION: When ATG pattern information F1 is supplied, the output of a scan path circuit is analyzed, and an invariable scan path flip-flop FF 4 allowing no scan path flip-flop holding time verification is searched. When an additional pattern F3 varying an output level of the invariable scan path flip-flop FF4 is added to the ATG pattern information F1, the verification of the holding time is allowed to be carried out in all the scan path flip-flop.
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