| 摘要 |
PURPOSE: A clock recovery circuit and a clock recovery method are provided to operate in a burst mode for recovering a clock signal from an early bit of input data. CONSTITUTION: A clock recovery circuit receives an input data stream and generates a frequency and phase aligned clock output. The clock recovery circuit substantially instantaneously adjusts a generated clock signal to phase changes in an incoming data stream. A gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The clock recovery circuit includes two PLL(Phase Locked Loop) circuits(PLL1,PLL2)(310,350). The first PLL(PLL1)(310) adjusts the frequency of a transmitter, and provides a bias voltage(CAP1)(325) to the second PLL(PLL2)(350) to indirectly initially tune the second PLL(350). The bias voltage(CAP1)(325) is applied to the second PLL(350) through a transmission gate or switch that is initially in a closed(short) position. The first PLL(310) drives the bias voltage(CAP2) of the second PLL(350), to align the frequency with the transmitter, until received data opens the transmission gate. A bias voltage(CAP2) is removed and the second PLL(350) operates without being controlled by the first PLL(310) so that the second PLL(350) oscillates in phase with the received data. Simultaneously, the received data starts the second oscillator(358) in the second PLL(350) so that the second oscillator(358) is in phase with the received data. The second PLL(350) then maintains this phase relationship between the second oscillator(358) and the received data.
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