| 摘要 |
PURPOSE: To solve the problem of the conventional PLL circuits having difficulty in outputting a clock having 90°phase difference. CONSTITUTION: Positive output of a PFD circuit 1 inputting an input clock CLK, and a feedback clock FBCLK is the positive input of a CP circuit 3. The negative output of a PFD circuit 2 for inputting the inversion clock of the clock CLK and the clock FBCLK is the negative input of the circuit 3.
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