发明名称 |
Hierarchical fully-associative-translation lookaside buffer structure |
摘要 |
A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB0 memory having a plurality of entries and a second-level TLB1 memory operatively coupled to the first level TLB0 memory. The second-level TLB1 memory also has a plurality of entries. Entries are placed in the TLB0 and TLB1 structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB0 treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB1 uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.
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申请公布号 |
US6418521(B1) |
申请公布日期 |
2002.07.09 |
申请号 |
US19980221230 |
申请日期 |
1998.12.23 |
申请人 |
INTEL CORPORATION |
发明人 |
MATHEWS GREGORY S.;MULLA DEAN A.;CHEONG FU JOHN WAI;SAILER STUART E. |
分类号 |
G06F12/10;G06F12/12;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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