发明名称 |
Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device |
摘要 |
A memory controller circuit arrangement and method utilize a tuning circuit that controls the timing of memory control operations via one or more programmable delay counters. Each counter is programmed to cycle a selected number of clock cycles to delay performance of a memory control operation to meet a predetermined timing parameter for a memory storage device coupled to the controller. Through the use of programmable delay counters, a variety of memory storage devices having varying timing parameters may be supported by the same memory controller design. Moreover, the use of programmable delay counters permit a single path of execution in a memory controller state machine to support any number of timing parameter variations for a particular timing characteristic, as well as multiple timing characteristics.
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申请公布号 |
US6438670(B1) |
申请公布日期 |
2002.08.20 |
申请号 |
US19980166004 |
申请日期 |
1998.10.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MCCLANNAHAN GARY PAUL |
分类号 |
G06F12/00;G06F13/16;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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