| 摘要 |
PURPOSE: An interface circuit between coprocessor type one-chip asynchronous microprocessors is provided to form an ASIC(Application Specific Integrated Circuit) for the high-speed telecommunication between two processors on one chip by making individual innermost processors directly access to an external memory. CONSTITUTION: The interface circuit comprises a first and a second processor memories(7a,7b), a first and a second processor memory controllers(8a,8b), a first and a second processors(9a,9b) having independent buses and memories by a first and a second interrupt controllers(10a,10b), and a first and a second processor IPC(Inter-Processor Communication) units(11a,11b) generating identical frequencies or different operating frequencies and controlling the accessing of the processor memories between the first and second processors. The first and second processors control the first and second IPC units by fetching an instruction from a following cycle or generating a nope signal.
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