| 摘要 |
PURPOSE: A method for manufacturing a transistor is provided to be capable of reducing sheet resistance and contact resistance by shortening junction depth of a source/drain. CONSTITUTION: The first and second gate pattern including a gate insulating layer(14), a polysilicon layer(15) and the first insulating layer(16), are formed on a substrate formed in a P-well and N-well region(12,13). After implanting lightly doped dopants, double sidewall spacers are formed at both sidewalls of the first and second gate pattern. A source and drain region(20a,20b) are formed in the substrate. An epitaxial layer(21) is formed on the source and drain region(20a,20b). After forming the second insulating layer(22) on the resultant structure, a contact hole is formed to expose the epitaxial layer(21) by selectively etching the second insulating layer. A metal film(23) is filled into the contact hole.
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