发明名称 ADDRESS DECODER FOR SELECTING SUB-BLOCK AND REFRESH OPERATING METHOD OF SDRAM USING ADDRESS DECODER
摘要 PURPOSE: An address decoder for selecting a sub-block and a refresh operating method of an SDRAM(Synchronous Dynamic Random Access Memory) using the address decoder are provided to reduce the peak current in the refresh operation by enabling sequentially a word line signal, a bit line sense amplifying signal, and an enable signal. CONSTITUTION: A buffering unit(31) receives a first sub-block selection address to buffer and output it. An inversion unit receives an external refresh signal to invert and output it. A first transmit gate(33) receives the external refresh signal, the output signal from the inversion unit, and a second sub-block selection address to output them. A delay unit delays the second sub-block selection address to output it. A second transmit gate(35) receives the second sub-block selection address delayed in the delay unit, the refresh signal, and the output signal from the inversion unit to output them.
申请公布号 KR20020072020(A) 申请公布日期 2002.09.14
申请号 KR20010011969 申请日期 2001.03.08
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, TAE YUN
分类号 G11C11/401;(IPC1-7):G11C11/401 主分类号 G11C11/401
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