Video signal processing system

摘要

It cannot be ensured that display setting changes are made at once in a system in which the number of display settings for a display processing apparatus is extremely large, an application is running under an operating system and display setting register change time is unpredictable from the application due to another task, or an internal configuration is incapable of immediately reflecting access from a host CPU to a display setting register. According to the present invention, outputs of a plurality of first display setting registers mapped into an address space for temporarily holding display setting data generated and outputted by a host CPU under control of a write control signal are connected to inputs of a plurality of second display setting registers holding display setting parameters referenced by display output module. Timing of a write into the second display setting registers is controlled by using a vertical sync signal and output from a display control register temporarily holding display control information generated and outputted by the host CPU, thereby allowing display settings to be reliably updated at once and allowing display outputs to be matched with the display settings without degrading system performance.