发明名称 |
Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device |
摘要 |
To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.
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申请公布号 |
US6479392(B2) |
申请公布日期 |
2002.11.12 |
申请号 |
US20010810577 |
申请日期 |
2001.03.19 |
申请人 |
HITACHI, LTD. |
发明人 |
YAMAZAKI KAZUO;KUNIYOSHI SHINJI;KUSAKARI KOUSUKE;IKEDA TAKENOBU;TADOKORO MASAHIRO |
分类号 |
H01L21/02;H01L21/28;H01L21/302;H01L21/3065;H01L21/3213;H01L21/8238;H01L27/092;H01L27/10;H01L29/43;H01L29/78;H01L29/786;(IPC1-7):H01L29/76;H01L29/94 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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