| 摘要 |
PURPOSE: A non-volatile memory device having a row decoder for reducing a size of layout is provided to minimize or reduce the size of layout and an area of a chip by improving a structure of the row decoder. CONSTITUTION: A plurality of sectors(300,300n) are formed with a plurality of floating gate memory cell transistors. A plurality of global row decoders(100,110,100n) are used for selecting global word lines by decoding some of external address signals. A plurality of division decoders(50,50n) are arranged at each sector in order to select divided word lines by decoding the remaining external address signals. A plurality of local row decoders(200,200n,210,210n,230,230n) are connected with global word lines of the global row decoders(100,110,100n) in order to activate the word lines of the selected sectors. A plurality of high voltage and erase voltage drivers(30,30n,40,40n) are used for generating high voltages and erase voltages according to sector address signals and applying the high voltages and the erase voltages to corresponding local row decoders. A plurality of sector selectors(10,10n) are used for generating sector selection signals according to sector address signals and applying the sector selection signals to local row decoders(200,200n,210,210n,230,230n). A plurality of bias drivers(20,20n) is used for generating bias voltages according to the sector address signals and applying the bias voltages to the local row decoders(200,200n,210,210n,230,230n).
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