发明名称 |
ON-CHIP INTERFERERS FOR STANDARDS COMPLIANT JITTER TOLERANCE TESTING |
摘要 |
Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation. |
申请公布号 |
HK1187166(A1) |
申请公布日期 |
2016.12.30 |
申请号 |
HK20130114394 |
申请日期 |
2013.12.30 |
申请人 |
BROADCOM CORPORATION |
发明人 |
Wang, John;Parthasarathy, Vasudevan |
分类号 |
H04B |
主分类号 |
H04B |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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