发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To surely test memory chips packed in a package in a semiconductor device in which a plurality of chips are packaged in the same package, and system is constituted by one package. SOLUTION: A logic chip and a memory chip accessed by the logic chip are packaged in one package. A pattern generating circuit of the logic chip is operated in a first test mode, to generate an internal test pattern for the memory chip. A pattern select circuit selects an internal test pattern output from the pattern generating circuit in a first test mode, and selects an external test pattern supplied through a test terminal in a second test mode to output the selected test pattern to the memory chip. The memory chip packaged in the package is tested with the internal test pattern (the first test mode) generated in the logic chip or the external test pattern (the second test mode) supplied from the outside according to the mode select signal.
申请公布号 JP2003084044(A) 申请公布日期 2003.03.19
申请号 JP20010279302 申请日期 2001.09.14
申请人 FUJITSU LTD 发明人 YAMAZAKI MASAFUMI;SUZUKI TAKAAKI
分类号 G01R31/28;G01R31/3183;G01R31/3185;G11C11/401;G11C11/406;G11C11/407;G11C29/00;G11C29/02;G11C29/12;(IPC1-7):G01R31/28;G01R31/318 主分类号 G01R31/28
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