发明名称 |
Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
摘要 |
A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.
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申请公布号 |
US6545892(B2) |
申请公布日期 |
2003.04.08 |
申请号 |
US20000741304 |
申请日期 |
2000.12.19 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
TAKANO SUSUMU;TAKAHASHI HIROYUKI;NIZAKA MINORU;KITANO TOMOHIRO |
分类号 |
G11C11/413;G11C8/10;H01L21/822;H01L21/8234;H01L27/04;H01L27/088;H01L27/10;H03K19/0948;H03K19/20;(IPC1-7):G11C5/02 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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