发明名称 |
Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor |
摘要 |
A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.
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申请公布号 |
US6551892(B2) |
申请公布日期 |
2003.04.22 |
申请号 |
US20010891438 |
申请日期 |
2001.06.25 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
PATELMO MATTEO;PIO FEDERICO |
分类号 |
H01L27/02;H01L27/07;(IPC1-7):H01L21/20 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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