DRAM array bit contact with relaxed pitch pattern

摘要

The invention provides improved DRAM cells using dual gate transistors, DRAM arrays and devices using DRAM cells as well as improved methods for manufacturing such cells, arrays and devices. The DRAM cells of the invention are characterized by the use of a shared bitline contact for each dual gate transistor. The DRAM arrays and devices of the invention are characterized by use of the DRAM cells of the invention and preferably by the use of a relaxed pitch layout for the bitline contacts. The techniques for manufacturing the DRAM arrays and devices of the invention are preferably characterized by use of a relaxed pitch bitline contact configuration which avoids the need for a critical mask.