发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To shorten a time required for a voltage stress acceleration test between complementary internal data lines. SOLUTION: Operation of a column system circuit (6) is controlled so that voltage stress is applied continuously to a complementary internal data line included in the column system circuit (6) at activation of a test mode signal (TM) from a row system control circuit (4) and a control circuit (8). Concretely, a write-driver driving a data line is kept forcedly at a non-activation state, and a sense amplifier is connected to an internal data line. Column selection operation is prohibited, the internal data line is driven forcedly and continuously according to the write-driver, or a voltage setting circuit is connected to the internal data line, and voltage stress of the internal data line is accelerated conforming to the voltage setting circuit of this internal data line at a test. Repeated data write operation is not required, voltage stress between complementary data lines can be applied continuously to the internal data line, a time required for the voltage stress between complementary data lines can be shortened. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003208799(A) 申请公布日期 2003.07.25
申请号 JP20020004628 申请日期 2002.01.11
申请人 MITSUBISHI ELECTRIC CORP 发明人 NAKAO HIROYUKI
分类号 G01R31/30;G01R31/28;G11C11/401;G11C29/06;G11C29/12;G11C29/14;(IPC1-7):G11C29/00 主分类号 G01R31/30
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