发明名称 |
INFORMATION RECORDING AND REPRODUCING APPARATUS, AND SIGNAL DECODING CIRCUIT AND METHOD |
摘要 |
PROBLEM TO BE SOLVED: To improve high density recording and reliability by shortening a preamble area and expanding a frequency locking range. SOLUTION: A timing recovery part 100 is provided with a buffer 62 for storing data in which a head reproduction signal has been made to be discrete by a fixed clock in order to detect and initially correct a phase offset and a frequency offset from a head area of reproduction data, a phase offset detector 70 for detecting the phase offset from the data head area in parallel with the operation for writing the data into the buffer 62, a frequency offset detector 72 for detecting the frequency offset from the data head area in parallel with the operation for writing the data into the buffer 62 at the same time, and a PLL for initially setting the correction state of the detected phase offset and frequency offset and subsequently executing a frequency locking and a phase locking in the head area while reading the data from the buffer 62. COPYRIGHT: (C)2004,JPO
|
申请公布号 |
JP2003281831(A) |
申请公布日期 |
2003.10.03 |
申请号 |
JP20020095505 |
申请日期 |
2002.03.29 |
申请人 |
FUJITSU LTD |
发明人 |
YAMAZAKI AKIHIRO;SUGAWARA TAKAO;TAKATSU MOTOMU;SAWADA MASARU |
分类号 |
G11B20/14;G11B5/09;G11B7/005;G11B20/10;G11B20/18;H04B3/06;(IPC1-7):G11B20/14 |
主分类号 |
G11B20/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|