| 摘要 |
PROBLEM TO BE SOLVED: To accurately reduce latchup caused by an applied trigger voltage to an OUT by a simple structure. SOLUTION: At least in one MOS transistor in a CMOS output circuit wherein a PMOS 10 and an NMOS 20 are connected in series between a VCC and a VSS, the number of a plurality of contacts 41, 51 arranged in series in the side of sources 10S, 20S is made fewer than the number of a plurality of contacts 42, 51 arranged in series in the side of drains 10D, 20D. Thereby, a resistance element (resistance means) is formed. Since the resistance element (resistance means) is connected to the sources 10S, 20S in series, latchup can be reduced accurately by a simple structure. COPYRIGHT: (C)2004,JPO
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