Process and structure for manufacturing plastic chip carrier

摘要

A process for forming a burrless castellation for a plastic chip carrier comprising forming one or more through holes in a substrate, plating the through holes with a metal to a thickness ranging from about 2 microns to about 6 microns, routing slots along the line extending through the through holes to produce half cylinder-shaped side-contact surfaces, and plating the half cylinder-shaped side-contact surfaces to a thickness in the range of 15 to 25 microns.