| 摘要 |
This invention consists of a hierarchical multiplexer-based interconnect architecture and is applicable to Field Programmable Gate Arrays, multi-processors, and other applications that require configurable interconnect networks. In place of traditional pass transistors or gates, multiplexers are used and the interconnect architecture is based upon hiearchical interconnection units. Bounded and predictable routing delays, compact configuration memory requirements, non-destructive operation in noisy environments, uniform building blocks and connections for automatic generation, scalability to thousands of interconnected elements, and high routability even under high resource utilization are obtained.
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