发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device that uniformly maintains the parasitic capacitance of the upper-layer wiring even when dummies are produced and, in addition, does not cause any short circuit between the wells even when a siliciding process is used. SOLUTION: This semiconductor device comprises a semiconductor substrate, an element separating area demarcating a plurality of active areas, and gate electrodes respectively formed on the surfaces of the active areas for forming a semiconductor element in each active area. This device also comprises an interlayer insulating film formed on the substrate to cover the gate electrodes, local wiring formed through the interlayer insulating film to connect the semiconductor element areas to each other, and a plurality of local wiring dummies formed in a state where the dummies are electrically separated from the local wiring. In addition, this device also comprises a plurality of lower-layer dummies each containing one dummy selected from among an active area dummy formed to pass through the element separating area, a laminated dummy of the active area dummy and a gate electrode dummy formed on the dummy, and a gate electrode dummy formed on the element separating area. Each local wiring dummy is disposed so that the dummy may not be connected to two of the lower-layer dummies. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004153091(A) 申请公布日期 2004.05.27
申请号 JP20020317758 申请日期 2002.10.31
申请人 FUJITSU LTD 发明人 NANJO RYOTA
分类号 H01L21/76;H01L21/3105;H01L21/3205;H01L21/762;H01L21/768;H01L21/82;H01L21/822;H01L21/8234;H01L23/52;H01L23/522;H01L27/02;H01L27/04;H01L27/08;H01L27/088;(IPC1-7):H01L21/320;H01L21/823 主分类号 H01L21/76
代理机构 代理人
主权项
地址