HIERARCHICAL QUADRANT BASED COVERAGE TESTING FOR RASTERIZATION

摘要

In embodiments described herein, graphics hardware is described to reduce the number of wasted clock cycles expended during rasterization and performs coverage test iteration in a cache coherent manner. An exemplary embodiment comprises block selection logic to select an initial block of pixels associated with edges of a primitive and edge determination logic to analyze the initial block of pixels to determine a set of fully covered quadrants of the initial block of pixels and analyze a block of pixels adjacent to the initial block of pixels to determine whether the block of adjacent pixels is void.