| 摘要 |
A graphics accelerator architecture in which instructing on a data stream which includes a mixture of scalars and short vectors (i.e. 2-, 3- or 4-vectors) are defined with an argument in the opcode which specifies the data type(s) being manipulated. The sequencer expands each of these opcodes on the fly to produce an appropriate series of instructions for the scalar processor to execute. This is particularly advantageous with the limited set of vector lengths handled in rendering operations.
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