Re-configurable single transformer quadrature voltage controlled oscillator

摘要

A quadrature voltage controlled oscillator (QVCO). The QVCO includes a first node for providing a first quadrature signal, a second node for providing a second quadrature signal, a third node for providing a third quadrature signal, and a fourth node for providing a fourth quadrature signal. The QVCO further includes a first coil connected between the first node and the second node and a second coil connected between the third node and the fourth node. The first coil and second coil are positively magnetically coupled.

主权项

1. A quadrate voltage controlled oscillator, comprising:
a first node for providing a first quadrature signal; a second node for providing a second quadrature signal; a third node for providing a third quadrature signal; a fourth node for providing a fourth quadrature signal; a first coil connected between the first node and the second node; a second coil connected between the third node and the fourth node, wherein the first coil and second coil are positively magnetically coupled; a first selectable conductive circuit coupled between the first node and the third node; a second selectable conductive circuit coupled between the second node and the fourth node; and selection circuitry for disabling the first and second selectable conductive circuits and in response providing a first differential signal between the first node and the second node and a second differential signal between the third node and the fourth node, wherein the first differential signal and the second differential signal are in phase with respect to one another; wherein the first selectable conductive circuit comprises:
a first transistor having a drain connected to the first node and a gate connected to the third node; anda second transistor having a drain connected to the third node, a gate connected to the first node, and a source connected to a source of the first transistor; and wherein the second selectable conductive circuit comprises:
a third transistor having a drain connected to the second node and a gate connected to the fourth node; anda fourth transistor having a drain connected to the fourth node, a gate connected to the second node, and a source connected to a source of the third transistor.