发明名称 |
Apparatus and method for assuming mastership of a bus |
摘要 |
The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.
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申请公布号 |
US7000131(B2) |
申请公布日期 |
2006.02.14 |
申请号 |
US20030713838 |
申请日期 |
2003.11.14 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
MILLER WILLIAM V.;DUNCAN RICHARD L. |
分类号 |
G06F1/32;G06F13/00;G06F13/36;G06F13/364 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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