发明名称 SEMICONDUCTOR DEVICE OR ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE
摘要 To provide a semiconductor device with a small circuit size and low power consumption or an electronic device including the semiconductor device and compressing a large volume of image data. A semiconductor device of a Hopfield neural network is formed using neuron circuits and synapse circuits. The synapse circuit includes an analog memory and a writing control circuit, and the writing control circuit is formed using a transistor including an oxide semiconductor in a channel formation region. Thus, data retention lifetime of the analog memory can be extended and refresh operation for data retention can be omitted, so that power consumption of the semiconductor device can be reduced. The semiconductor device enables judgement whether learned image data and arbitrary image data match, are similar, or mismatch by comparing video data. Thus, motion compensation prediction, which is one of data compression methods, can be employed for image data.
申请公布号 US2017063351(A1) 申请公布日期 2017.03.02
申请号 US201615245366 申请日期 2016.08.24
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 KUROKAWA Yoshiyuki
分类号 H03K3/356;H02M3/07;H04N19/42;H01L29/786 主分类号 H03K3/356
代理机构 代理人
主权项 1. A semiconductor device comprising first to fourth circuits, wherein the first circuit comprises a first charge pump circuit, a second charge pump circuit, an analog memory, and a logic circuit, wherein the first charge pump circuit and the second charge pump circuit each include a first transistor, wherein the first transistor comprises an oxide semiconductor in a channel formation region, wherein the logic circuit comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the second circuit comprises a third input terminal and a third output terminal, wherein the third circuit has a same circuit structure as the second circuit, wherein the third circuit comprises a fourth input terminal and a fourth output terminal, wherein the fourth circuit comprises a fifth input terminal, a sixth input terminal, and a fifth output terminal, wherein the first input terminal is electrically connected to the fifth input terminal and the third output terminal, wherein the second input terminal is electrically connected to the fourth output terminal, wherein the first output terminal is electrically connected to the first charge pump circuit, wherein the second output terminal is electrically connected to the second charge pump circuit, wherein the analog memory is electrically connected to the first charge pump circuit, the second charge pump circuit, and the sixth input terminal, and wherein the fifth output terminal is electrically connected to the fourth input terminal.
地址 Atsugi-shi JP