发明名称 Information processing apparatus, method for controlling information processing apparatus, non-transitory recording medium storing control tool, host device, non-transitory recording medium storing performance evaluation tool, and performance evaluation method for external memory device
摘要 According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.
申请公布号 US9594611(B2) 申请公布日期 2017.03.14
申请号 US201414178654 申请日期 2014.02.12
申请人 Kabushiki Kaisha Toshiba 发明人 Hashimoto Daisuke
分类号 G06F15/177;G06F11/00;G06F11/34;G06F11/14;G06F11/07;G06F9/44 主分类号 G06F15/177
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. An information processing device comprising: a semiconductor memory device including: a nonvolatile semiconductor memory including memory cells for storing data, and configured to electrically erase, in a first unit, data stored in the memory cells, the first unit including the plurality of memory cells,a volatile semiconductor memory,a controller,a temperature sensor, anda host interface; and a host device configured to transmit a read command and write command to the semiconductor memory device, wherein each of the nonvolatile semiconductor memory and the volatile semiconductor memory is configured to store first information for specifying a physical address of the nonvolatile semiconductor memory corresponding to logical address information received from the host device via the host interface, when receiving the write command from the host device via the host interface, the controller is configured to generate a correction code by using data received from the host device and to store the data and the correction code in the nonvolatile semiconductor memory, and when receiving the read command from the host device via the host interface, based on data and a corresponding correction code read from the nonvolatile semiconductor memory using the first information, the controller is configured to correct the read data, the nonvolatile semiconductor memory is configured to further store: second information based on a total number of pieces of write data received according to the write command received from the host device,third information based on a total number of pieces of data read from the nonvolatile semiconductor memory according to the read command received from the host device,fourth information related to a number of pieces of data that have not been corrected by using the corresponding correction code among data read from the nonvolatile semiconductor memory,fifth information indicating, with the first unit, information corresponding to a number of memory cells in the nonvolatile semiconductor memory that are determined to be unable to write data therein,sixth information corresponding to a number of the memory cells in the nonvolatile semiconductor memory that are determined to be able to write data therein, andseventh information based on a temperature measured by using the temperature sensor; the host device is configured to display, on a display device connected to the host device, first status information of the nonvolatile semiconductor memory based on the second information or the third information, second status information of the nonvolatile semiconductor memory based on the fourth information or the fifth information, and third status information of the nonvolatile semiconductor memory based on the seventh information, and the semiconductor memory device is configured to erase, in the first unit, data stored in a corresponding physical address based on a command and logical address information received from the host device, and to change the sixth information.
地址 Tokyo JP