发明名称 Semiconductor memory device which stores plural data in a cell
摘要 A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
申请公布号 US9627048(B2) 申请公布日期 2017.04.18
申请号 US201615175806 申请日期 2016.06.07
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Shibata Noboru;Tanaka Tomoharu
分类号 G11C11/34;G11C11/56;G11C16/04;G11C16/12;G11C16/34;G11C16/10 主分类号 G11C11/34
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, the memory cells being connected to a word line, the memory cells being connected to bit lines, respectively, and each of the memory cells being capable of storing n values (n is a natural number equal to or larger than 3); and a control circuit which controls potentials of the word line and the bit lines according to input data and writes data to the memory cells, wherein the control circuit executes first to k-th write sequences (k is a natural number equal to or larger than 2) for the memory cells, each write sequence including a plurality of program operations and a plurality of verify operations for verifying threshold voltages of the memory cells, the program operations and the verify operations being repeated alternately, data being written to the memory cells together, and each of the memory cells being set to one of the n values in the write sequences, the control circuit raises a program voltage in increments of ΔVpgm in the program operations, threshold distributions in the first to k-th write sequences get narrower in order, and ΔVpgm in the first k-th write sequences fulfill the following expression: ΔVpgm in the first write sequence>ΔVpgm in the second write sequence>ΔVpgm in the k-th write sequence.
地址 Minato-ku JP