Systems, methods, and devices for parallel read and write operations

摘要

Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

主权项

1. A device comprising:
a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array, the first transmission device configured to selectively couple the global bit line to the local bit line; a first device coupled to the local bit line and a sense amplifier, the first device configured to selectively couple the local bit line to the sense amplifier in response to a low voltage operation, wherein the first device is further configured to decouple the local bit line from the sense amplifier in response to a high voltage operation or the memory unit being unselected; and a second device coupled to the local bit line and an electrical ground, the second device configured to selectively couple the local bit line to the electrical ground in response to the memory unit being unselected, and wherein the second device is further configured to decouple the local bit line from the electrical ground in response to the high voltage operation or the low voltage operation.