Lower power sense amplifier for reading non-volatile memory cells

摘要

A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state.

主权项

1. A sense amplifier, comprising:
a first and a second detection input; a latch circuit including a first section configured to supply a first data signal and a second section coupled to the first section and configured to supply a second data signal; a P-channel first control transistor configured to electrically supply the first section with a first supply voltage, and having a gate terminal configured to receive a first control signal and linked to the first detection input; a P-channel second control transistor configured to electrically supply the second section with a second supply voltage, and having a gate terminal configured to receive a second control signal and linked to the second detection input; a first control circuit configured to reduce the first control signal to a sufficiently low voltage to put the first control transistor to an on state in response to the first control signal reaching a first reference voltage; and a second control circuit configured to reduce the second control signal to a sufficiently low voltage to put the second control transistor to the on state in response to the second control signal reaching a second reference voltage, the latch circuit being configured to supply the first data signal in response to being activated by the first control transistor being in the on state and being configured to supply the second data signal in response to being activated by the second control transistor being in the on state.