| 摘要 |
An analog-programmed, successive-approximations, analog to digital/digital to analog (A to D, D to A) converter circuit wherein an unknown analog voltage input signal is converted to a digital output signal. The converter includes an analog programmer comprising a plurality of binary-weighted, series-connected resistors in circuit with a known reference signal to provide weighted, known input signals to each of a plurality of differential comparators. A sweep signal, in circuit with the unknown analog signal, provides a second input to the differential comparators of the analog programmer. The programmer comparators are sequentially switched at known signal magnitudes from one logical state to another to provide a plurality of discrete signals. The changes in the respective output states of the comparators provide a first data input to corresponding flipflop circuits in a data register. A predetermined digital output state of the data register will enable a corresponding analog summing path of a precision D to A converter. Each analog summing path comprises a diode in circuit with a binary-weighted resistor. A current summing amplifier provides a signal to the input of a data feedback comparator which indicates the relative magnitudes of the known input signal and the unknown test signal. When the magnitude of the unnown input signal exceeds the magnitude of a test signal in the circuit, the data feedback comparator produces an output having a predetermined logical state. That predetermined output from the data feedback comparator will cause a predetermined flipflop circuit in the output data register to enable the corresponding analog summing path in the converter circuit means. Conversely, when the magnitude of the input signal is less than the magnitude of the test signal, the corresponding converter analog summing path will remain in its disenabled state. By sequentially switching the programmer comparators at predetermined intervals, the unknown input signal is determined by successively approximating the magnitude of the input signal by successively enabling the signal summing paths in the converter section. |
