发明名称 PHASE LOCKED LOOP
摘要 A hybrid digital phase locked loop is disclosed to recover an isochronous clock from a "stuffed" multiplexed input signal as found in an asynchronous PCM demultiplexer. A low frequency voltage controlled multivibrator is controlled by the output of a phase comparator. The phase comparator is coupled to the input signal and the output signal of a distributor. The distributor is controlled by the multivibrator to sequentially switch a multiphase output signal of a crystal oscillator to provide the output signal of the distributor. This arrangement overcomes the requirement of a voltage controlled crystal oscillator per channel group in the demultiplexer.
申请公布号 US3731219(A) 申请公布日期 1973.05.01
申请号 USD3731219 申请日期 1972.06.13
申请人 STANDARD ELECTRIC CORP,US 发明人 MADER H,CH;HOCHREUTINER R,GB
分类号 H04J3/07;(IPC1-7):H03B3/04 主分类号 H04J3/07
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