发明名称 Semiconductor device including a buffer layer structure for reducing stress
摘要 A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
申请公布号 US9515043(B2) 申请公布日期 2016.12.06
申请号 US201615084038 申请日期 2016.03.29
申请人 SEIKO EPSON CORPORATION 发明人 Yuzawa Takeshi;Tagaki Masatoshi
分类号 H01L29/40;H01L21/44;H01L23/00;H01L23/528 主分类号 H01L29/40
代理机构 Oliff PLC 代理人 Oliff PLC
主权项 1. A semiconductor device comprising: a semiconductor chip having a laminating structure and a pad; a wiring that is included in the semiconductor chip, the wiring having a first wiring portion and a second wiring portion, a first width of the first wiring portion being different from a second width of the second wiring portion, the wiring has a junction between the first wiring portion and the second wiring portion; a conductive material that is formed in a position between the junction and the pad; and a contact part for making contact with a diffusion layer and the wiring; and a passivation film that covers a part of the pad, wherein, when the laminating structure is viewed with the semiconductor device oriented with the pad at the top portion, the pad is disposed above the junction, the diffusion layer is formed below the wiring, and the conductive material is arranged in overlapping relation with the pad, the junction, the contact part and the diffusion layer in a plan view from above the pad.
地址 Tokyo JP