Parallel data switch

摘要

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

主权项

1. An interconnect apparatus comprising:
a plurality of logic units configured in circuitry in one or more integrated circuits and configured in an arrangement of triplets including a logic unit LA, a logic unit LC, and a logic unit LD, wherein the logic unit LA and the logic unit LC are configured to send data to the logic unit LD and the logic unit LC has priority over the logic unit LA for sending the data to the logic unit LD; a plurality of buses coupling the plurality of logic units; and at least one switch configured to control communication of the data in packets, the packets apportioned into subpackets and the packets specifying a target logic unit to receive the packet, the at least one switch controlling the communication of the data wherein for a first packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet PKT specifying a target indicating an action of actions including:
the logic unit LC sends a subpacket of a packet to the logic unit LD and the logic unit LA does not send a subpacket of the first packet PKT to the logic unit LD;the logic unit LC does not send a subpacket of a packet to the logic unit LD and the logic unit LA sends a subpacket of the first packet PKT to the logic unit LD; andthe logic unit LC does not send a subpacket of a packet to the logic unit LD and the logic unit LA does not send a subpacket of the first packet PKT to the logic unit LD, wherein for the logic unit LA positioned to send packets to a plurality of logic units including the logic unit LD, and the logic unit LA controls an action wherein:
Case 1:
the logic unit LA determines that the logic unit LD is the logic unit most appropriate to receive the first packet PKT of: the logic unit LC sends a packet to the logic unit LD and the logic unit LA sends the first packet PKT to a logic unit LG distinct from the logic unit LD; and no logic unit with higher priority than the logic unit LA to send packets to the logic unit LD sends a packet to the logic unit LD and the logic unit LA sends a subpacket of the first packet PKT to the logic unit LD; GP andCase 2:
the logic unit LA determines that sending the first packet PKT to the logic unit LD is unacceptable, and the logic unit LA sends a subset of the first packet PKT to the logic unit LG distinct from the logic unit LD; andfor the logic unit LA receiving a first subpacket of the first packet PKT at a time Ts:
if the logic unit LA sends the first subpacket of the first packet PKT to the logic unit LD, then logic unit LD receives the first subpacket of the first packet PKT at a time Ts+1if the logic unit LA sends the first subpacket of the first packet PKT to the logic unit LG external to the triplet, then the first subpacket of the first packet PKT passes through a delay unit DA and arrives at the logic unit LG at a time Ts+2 andif the logic unit LC sends a first subpacket of a second packet to the logic unit LD and the first subpacket of the second packet blocks the first packet PKT from traveling to the logic unit LD, then the first subpacket of the second packet arrives at the logic unit LD at time Ts+1.